1. Field of the Invention
This invention relates to a circuit, system and method for avoiding a non-desired output from a latch and, in particular, to a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A latch is typically understood to be any device that can store information. A popular form of a latch is alternatively known as a xe2x80x9cflip-flop.xe2x80x9d A latch or flip-flop is designed to produce an output that is stable in one of two logic states. The output logic level will remain until the input to the latch undergoes a change in logic level.
Output from the latch can be at a xe2x80x9ctrue,xe2x80x9d xe2x80x9con,xe2x80x9d xe2x80x9chigh,xe2x80x9d or xe2x80x9c1xe2x80x9d logic level or, alternatively, at a xe2x80x9cfalse,xe2x80x9d xe2x80x9coff,xe2x80x9d xe2x80x9clow,xe2x80x9d or xe2x80x9c0xe2x80x9d logic level. For convenience in relating relativity to logic level, the former logic level, logical 1, is assumed to be the most positive voltage and the latter logic level, logical 0, represents the most negative voltage value. This relationship is known as positive logic and is used as a convention herein.
There are several types of latches used to store logical 1 or logical 0 logic levels. Latches can be classified as either clocked or non-clocked. If clocked, a clock pulse controls the times at which outputs from the latch can transition. For example, a toggle latch will impart toggling action on the output of the latch during transitions of the clock pulse whenever the toggling input is at a logical 1 logic level. Other forms of latches may not require any clock input whatsoever. For example, a set/reset (SR) latch causes an output from the latch to be set or reset depending on the logic levels of signals placed on the set and reset inputs.
Regardless of whether a latch is clocked or not, there are generally two complimentary outputs produced from a latch. The complimentary outputs are oftentimes referred to as differential outputs, in that while one output is at a logical 1 level, the other output is at a logical 0 level (i.e., complimentary to the former logic level). The complimentary outputs are oftentimes labeled Q and Qxe2x80x2. When one output is at the logical 1 state, the other output is always at a logical 0 state. In this manner, if the latch changes state, then both Q and Qxe2x80x2 change. A latch is considered to be xe2x80x9csetxe2x80x9d when Q is in a logical 1 state and Qxe2x80x2 is in a logical 0 state. Conversely, the latch is xe2x80x9cresetxe2x80x9d when Q is in a logical 0 state, and Qxe2x80x2 is in a logical 1 state. Generally, a latch is reset in anticipation of it being subsequently set to store binary information.
A simple example of a non-clocked set/reset (SR) latch is shown in FIG. 1. In particular, FIG. 1 illustrates a NAND gate SR latch 10a and a NOR gate SR latch 10b. Latch 10a comprises a pair of cross-connected NAND gates 12 and 14, while latch 10b comprises a pair of cross-connected NOR gates 16 and 18. Latches 10 each have two inputs labeled S and R (for set and reset) and, therefore, are classified as SR latches. Each latch 10 also has a pair of complimentary outputs labeled Q and xe2x80x9cQ barxe2x80x9d (or Qxe2x80x2).
Referring to the truth tables 20a and 20b, logic levels are shown for outputs Q and Qxe2x80x2 corresponding to inputs S and R. Truth table 20a represents the operation of the NAND gate SR latch 10a, while truth table 20b represents the operation of the NOR gate SR latch 10b. Referring to truth table 20a, it can be seen that if the S input goes to a logic 0 level, then the latch will go to its set state (Q equals a logic 1 level), and will remain in that state until reset. When the R input goes to a logic 0 level, then the latch will go to its reset state and stay there until it is set again. Thus, an SR latch changes state upon sensing a change in state at the S or R inputs, and stores the results of the change until the opposite input is activated. Truth table 20b indicates that the NOR gate SR latch will transition to a set state whenever the S input goes to a logic 1 level, and will transition to a reset state when the R input goes to a logic 1 level.
The set and reset states are noted as xe2x80x9cSETxe2x80x9d and xe2x80x9cRST,xe2x80x9d as shown in FIG. 1. In addition to the set and reset states, two special conditions of interest exist for an SR latch. First, whenever both of the S and R inputs are at a logic 1 level (for the NAND gate embodiment 10a) or at a logic 0 level (for the NOR gate embodiment 10b) no change is made to the complimentary outputs. This state is noted as a memory (xe2x80x9cMEMxe2x80x9d) state since the outputs retain their previous logic levels. However, if both of the set and reset inputs are at a logic 0 level (for the NAND gate embodiment 10a) or at a logic 1 level (for the NOR gate embodiment 10b), then the complimentary output conductors enter the same state: either logic 1 level for the NAND gate latch 10a or a logic 0 level for the NOR gate latch 10b. Having the same logic level on the complimentary output is not desired and, accordingly, this state is labeled xe2x80x9cND.xe2x80x9d
A non-desired output state is to be prevented for at least two reasons. First, the complimentary outputs are generally used elsewhere in the circuit subsystem. That subsystem depends on the Q output being 180xc2x0 out of phase with the Qxe2x80x2 output. Having the Q and Qxe2x80x2 outputs at the same logic levels could be catastrophic to the operation of any load coupled to receive complimentary inputs. Second, the non-desired state can produce non-deterministic logic levels. For example, if a transistor within logic gate 14 is made having stronger drive outputs than a transistor within NAND gate 12, then even though the set and reset inputs are at a logic 0 level, the Q output may skew to a differential logic level from that of the Qxe2x80x2 output. This may indicate a set state when, in fact, the set and reset inputs are not in a set condition (e.g., the set input being at a logic 0 level and the reset input being at a logic 1 level for the exemplary NAND gate example).
Therefore, most designers attempt to avoid placing a latch in a non-desired state. However, there may be times when the non-desired state is difficult to avoid and is uncontrollably dependent on the set and reset input conditions. Thus, it would be desirable to introduce an improved SR latch that can avoid a non-desired state regardless of the SR input values. In addition to avoiding a non-desired state, it would be further desirable to provide an improved selector circuit that is easily programmed to force the latch to output complimentary signals regardless of input signals sent to the latch.
The problems outlined above are in large part solved by an improved latch including an improved, programmable selector circuit. Preferably, the latch is an SR latch that need not be clocked, and can avoid non-desired states. The latch can be implemented as a quasi-NAND gate or quasi-NOR gate configuration. In addition to the set and reset inputs, the latch receives programmable inputs via the programmable selector circuit. Depending on the logic value of the programmable inputs, the latch can be easily programmed to give priority to the set input, the reset input, or both.
The programmed inputs are fed onto gate conductors or base conductors of respective transistors coupled in series with the transistors that receive the set and reset inputs. The series-connected resistors are also cross-coupled with and parallel to corresponding transistors within a memory or latch cell. The pairs of series-connected transistors can, therefore, form a prioritizer or priority encoder according to one embodiment. The purpose of the memory element is to simply store the complimentary outputs produced by the prioritizer and retain those outputs on the output conductors of the latch. Furthermore, the selector circuit is used to select xe2x80x9cset barxe2x80x9d (Sxe2x80x2), xe2x80x9creset barxe2x80x9d (Rxe2x80x2), or both setxe2x80x2 and resetxe2x80x2 to be placed on the programmable inputs of the prioritizer.
The latch can be implemented using solely n-type (NMOS) transistors or bipolar (NPN) transistors. Alternatively, the latch can use p-type (PMOS) transistors or PNP transistors. If implemented with the latter form of transistors, then the set and reset inputs can receive complimentary set and reset values, while the programmable inputs can receive set, reset, or set and reset values. For example, use of PMOS transistors rather than NMOS transistors merely indicates that the values on the set, reset, and programmable inputs are switched to the corresponding complimentary values. This also applies to switching between either a sourcing power supply or ground. If NMOS transistors are used, then a sourcing power supply (VDD) is used on one programmable input. Conversely, a ground (VSS) is used in lieu of VDD if PMOS transistors are used.
According to one embodiment, a latch includes a selector circuit having a pair of input conductors and a prioritizer coupled to an output of the selector circuit. The selector circuit can receive a pair of programmable signals forwarded to the pair of input conductors, while the prioritizer can receive a pair of set and reset signals of substantially the same logic value (i.e. both set and reset signals have logic 1 values, or alternatively, both have logic 0 values). In addition, the selector circuit is adapted to output a pair of voltage values to the prioritizer so as to configure the prioritizer into a set-dominant state, a reset-dominant state, or a memory-dominant state. The selector circuit is thereby adapted to program the latch not only to avoid the non-desired state, but also to force the latch into one of three states dependent on the programmable signals sent to the selector circuit.
For example, the selector circuit may output a voltage value that is complementary to the set signal during times when the programmable signals are of substantially dissimilar logic value. In such an example, the voltage value produced by the selector circuit would configure the prioritizer into a set-dominant state. On the other hand, to configure the prioritizer into a reset-dominant state, the selector circuit may output a voltage value that is complementary to the reset signal during times when the programmable signals are of substantially dissimilar logic value. Alternatively, the selector circuit may output a pair of voltage values complementary to the pair of set and reset signals during times when the programmable signals are of substantially similar logic value. In this example, the pair of voltage values would configure the prioritizer into a memory-dominant state, such that the prioritizer would produce a pair of complementary logic values upon the output conductors of the latch even when the set and reset signals have similar logic values. In other words, the latch will substantially avoid the non-desired state regardless of the latch input values.
According to another embodiment, a system for latching complementary voltage values includes a prioritizer, a selector circuit, and an execution unit. The prioritizer is coupled to receive set and reset signals. In addition, the selector circuit can receive programmable bits from the execution unit, which is coupled to the selector circuit to set each of the programmable bits to either a logic 1 or logic 0 value. In this manner, the selector circuit is adapted to configure the prioritizer to produce complementary logic voltage values at the output of the prioritizer regardless of whether the set and reset signals are at the same or dissimilar logic voltage values. Thus, the logic value of the a programmable bits determines whether the set signal, the reset signal, or the previous set and reset signals are latched upon the output conductors of the prioritizer, and thus, the output conductors of the latch.
According to yet another embodiment, a method is provided for preventing a non-desired output from a latch. The method includes receiving a similar logic voltage value on set and reset conductors, while receiving programmable voltage values that are adapted to configure the latch output. Depending on the programmable voltage values, the method further includes placing upon a pair of output conductors of the latch either (i) the logic voltage value on the set conductor and its complementary logic voltage value, (ii) the logic voltage value on the reset conductor and its complementary logic voltage value, or (iii) the logic voltage values on the set and reset conductors preceding the step of receiving a similar logic voltage value on set and reset conductors. In this manner, the method includes programming the voltage values to fix the output of the latch as a set-dominant latch output, a reset-dominant latch output, or a memory-dominant latch output.